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Job Opportunity:

DFT Engineer

 
Posted   Apr 18  
 
Entry Number   82196  
 
Job Title   DFT Engineer  
 
Job Description   Looking for experienced hands-on DFT (Design For Test) engineers for low power, high performance and cutting edge SoCs
• Participate in definition and driving both chip level and block DFT methodology
• Responsible for ATPG (Automatic Test Pattern Generation) implementation and simulation based on gate-level netlist
• Work closely with integration and backend teams for scan chain insertion and timing analysis.
• Work closely with the global product and test engineers to define test solution for high speed IPs, debug and solve scan pattern failures in tester.

Requirements:

• BSc. In Electrical engineering
• Above 3 years of DFT experienced from VLSI companies
• Strong knowledge in DFT techniques for high performance SoC
• Experience in industrial ATPG tools, Verilog simulation and scan debug tools
• Experience in memory BIST and JTAG interfaces – Advantage
• Strong understanding in Logic Design, Verilog (RTL and GLV), verification, and static timing analysis
• Experience in silicon bring-up, debug, and validation of DFT features
• Good communication & teamwork skills
 
 
Operational Sector   Engineering – Electrical, Electronics, Mechanical  
 
Position Code   50338  
 
Region   Center  
 

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