||Backend/Layout for the MWG-VLSI-Backend group includes RTL to GDSII flow implementation and verification.
The wireless organization has multiple products which included different optimized silicon with different coms.
The Backend Group implement, verify and Tape-Out according to product plan and milestones, using industry implementation and verification tools with unique internal environments.
The Backend Group responsible to the RTL/Netlist implementation through floorplan, placement, CTS, Routing and optimization using synopsys ICC flow as well as verification using Synopsys, Cadence, Mentor signoff tools.
Physical verification (DRC/LVS) using Calibre
IRdrop/EM analysis using apache
Formal verification using LEC
Static timing analysis using prime-time, prime-time-SI - Advantage
RTL/Netslist to GDSII (floorplan, Placement, CTS, Routing, Timing optimization) using ICC – Advantage.